This invention relates to a method of manufacturing a semiconductor device, and in particular, relates to a method of manufacturing a semiconductor device which has a plurality of MIS (Metal Insulator Semiconductor) transistors having various thresholds.
An LSI (Large Scale Integrated circuit) is known as a typical semiconductor device and generally comprises a large number of MOS (Metal Oxide Semiconductor) transistors which are a sort of the MIS transistors and which are superior in integration. Such an MOS LSI is widely applicable to various electronic equipment including an information equipment because manufacturing costs of the MOS LSI can be lowered by increasing a degree of the integration.
Recently, an LSI that memories and logic units (or logic circuits) are merged in a single semiconductor chip and that is categorized into a group called an SOC (System On Chip) was developed and could realize desired functions singly. For example, the LSI is applied to a mobile information apparatus. The LSI for the mobile information apparatus is designed so as to save power consumption and to be operated by the lowest possible voltage, because a power source is a battery in the mobile information apparatus.
In the LSI categorized into the SOC group, each of the logic units is made by a CMOS (Complementary MOS) process and comprises n-type MOS transistors and p-type MOS transistors. The n-type MOS transistors and the p-type MOS transistors have various thresholds so that the LSI carries out the desired functions.
Generally, reduction of a threshold is necessary to heighten an operation speed of a transistor. Moreover, increase of the threshold is necessary to reduce both of leakage current and power consumption of the transistor. Consequently, the n-type and p-type MOS transistors in each of the logic units have the various thresholds according to their purpose.
If the n-type MOS transistors have three levels for their thresholds in the logic unit, three times of a lithography process are necessary to form a well and channel regions of the n-type MOS transistors. Similarly, if the p-type MOS transistors have three levels for their thresholds in the logic unit, additional three times of the lithography process are necessary to form a well and channel regions of the p-type MOS transistors. Thus, a large number of processes are necessary to manufacture the semiconductor device such as the LSI categorized into the SOC group.
In the meantime each MOS transistor has junction capacitance between each of a source region and a drain region and a substrate. In a case where a rapid operation is desired in the MOS transistor, it is desirable that the junction capacitance is the smallest as possible.
It is therefor an object of this invention to provide a method of manufacturing a semiconductor device which can be reduce the number of times of lithography process.
It is another object of this invention to provide a structure of a semiconductor device which have MOS transistors having various thresholds and which is easy to manufacture.
It is still another object of this invention to provide a structure of a semiconductor device which has MOS transistors and has small junction capacitance between each of a source region and a drain region and a substrate in at least one of the MOS transistors.
Other object of this invention will become clear as the description proceeds.
According to a first aspect of this invention, a semiconductor device has first, second and third MIS transistors on a semiconductor substrate. The first MIS transistor has a first threshold. The second MIS transistor has a second threshold higher than the first threshold. The third MIS transistor has a third threshold higher than the second threshold. A method of manufacturing the semiconductor device comprises the steps of depositing a first mask on the semiconductor substrate at a first area for the first MIS transistor, introducing first impurities into the semiconductor substrate to form wells at second and third areas for the second and the third MIS transistors, successively, introducing second impurities into the wells to form first threshold adjustment regions for the second threshold, depositing a second mask on the semiconductor substrate at the second area for the second MIS transistor after removing the first mask, and introducing third impurities into the semiconductor substrate to form second threshold adjustment regions for the first threshold at the first and the third areas. One of the second threshold adjustment regions serves as a third threshold adjustment region for the third threshold together with one of the first threshold adjustment regions at the third area.
According to a second aspect of this invention, a semiconductor device has first, second and third MIS transistors in a semiconductor substrate. The first MIS transistor has a first threshold. The second MIS transistor has a second threshold higher than the first threshold. The third MIS transistor has a third threshold higher than the second threshold. A method of manufacturing the semiconductor device comprises the steps of defining first, second and third areas corresponding to the first, the second and the third MIS transistors, respectively, on a surface of the semiconductor substrate, depositing a first mask having first and second opening windows corresponding to the second and the third areas, respectively, on the surface of the semiconductor substrate, introducing first impurities into the semiconductor substrate through said first and the second opening windows to form wells at the second and the third areas at the same time, successively introducing second impurities into the wells through the first and the second opening windows to form first threshold adjustment regions for the second threshold at the same time, completely removing the first mask from the surface of the semiconductor substrate, depositing a second mask having third and fourth opening windows corresponding to the first and third areas, respectively, on the surface of the semiconductor substrate, and introducing third impurities into the semiconductor substrate through the third and the fourth opening windows to form second threshold adjustment regions for the first threshold at the same time. One of the second threshold adjustment regions serves as a third threshold adjustment region for the third threshold together with one of the first threshold adjustment regions at the third area.
According to a third aspect of this invention, a semiconductor device has first, second and third MOS transistors having a first conductive type and has fourth, fifth and sixth MOS transistors having a second conductive type different from the first conductive type. The first and the forth MOS transistors forms a first CMOS transistor having a first threshold. The second and the fifth MOS transistors forms a second CMOS transistor having a second threshold higher than the first threshold. The third and the sixes MOS transistors forms a third CMOS transistor having a third threshold higher than the second threshold. A method of the semiconductor device comprises the steps of defining first through sixth areas corresponding to first through sixth MOS transistors, respectively, on a surface of the semiconductor substrate, depositing a first mask having first and second opening windows corresponding to the second and the third areas, respectively, on the surface of the semiconductor substrate, introducing first impurities of the second conductive type into the semiconductor substrate through the first and the third opening windows to form first wells in the second and the third areas at the same time, successively introducing second impurities of the second conductive type into the first wells through the first and the second opening windows to form first threshold adjustment regions for the second threshold at the same time, completely removing the first mask from the surface of the semiconductor substrate, depositing a second mask having third and fourth opening windows corresponding to the first and the third areas, respectively, on the surface of the semiconductor substrate, introducing third impurities of the second conductive type into the semiconductor substrate through the third and the fourth opening windows to form second threshold adjustment regions for the third threshold at the same time, completely removing the second mask from the surface of the semiconductor substrate, depositing a third mask having fifth and sixth opening windows corresponding to the fourth and the sixth areas, respectively, on the surface of the semiconductor substrate, introducing fourth impurities of the first conductive type into the semiconductor substrate through the fifth and the sixth opening windows to form second wells in the fourth and the sixth areas at the same time, successively introducing fifth impurities of the first conductive type into the second wells through the fifth and the sixth opening windows to form fourth threshold adjustment regions for the first threshold at the same time, completely removing the third mask from the surface of the semiconductor substrate, depositing a fourth mask having seventh and eighth opening windows corresponding to the fifth and sixth areas, respectively, on the surface of the semiconductor substrate, introducing sixth impurities of the first conductive type into the semiconductor substrate through the seventh and the eighth opening windows to form third wells in the fifth and the sixth areas at the same time, and successively introducing seventh impurities of the first conductive type into the semiconductor substrate through the seventh and the eighth opening windows to form fifth threshold adjustment regions for the second threshold in the third wells at the same time. One of the second threshold adjustment regions serves as a third threshold adjustment region for the third threshold together with one of the first threshold adjustment regions at third area. One of the fifth threshold adjustment regions serves as a sixth threshold adjustment region for the third threshold together with one of the fourth threshold adjustment regions at sixth area.
According to a fourth aspect of this invention, a semiconductor device comprises a first MIS transistor having a first source region, a first drain region, a first threshold adjustment region, and a first threshold. A second MIS transistor has a second source region, a second drain region, a second threshold adjustment region, and a second threshold higher than the first threshold. A third MIS transistor has a third source region, a third drain region, a third threshold adjustment region, and a third threshold higher than the second threshold. The first threshold adjustment region is apart from both of the first source region and the first drain region. The second threshold adjustment region is in contact with both of the second source region and the second drain region. The third threshold adjustment region is in contact with both of the third source region and the third drain region.
According to a fifth aspect of this invention, a semiconductor device comprises a first MOS transistor having a first source region, a first drain region, a first threshold adjustment region, and a first conductive type. A second MOS transistor has a second source region, a second drain region, a second threshold adjustment region, and the first conductive type. A third MOS transistor has a third source region, a third drain region, a third threshold adjustment region, and the first conductive type. A fourth MOS transistor has a fourth source region, a fourth drain region, a fourth threshold adjustment region, and a second conductive type, and forms a first CMOS transistor having a first threshold together with the first MOS transistor. A fifth MOS transistor has a fifth source region, a fifth drain region, a fifth threshold adjustment region, and the second conductive type, and forms a second CMOS transistor having a second threshold higher than the first threshold together with the second MOS transistor. A sixth MOS transistor has a sixth source region, a sixth drain region, a sixth threshold adjustment region, and the second conductive type, and forms a third CMOS transistor having a third threshold higher than the second threshold together with the third MOS transistor. The first threshold adjustment region is apart from both of the first source region and the first drain region. The second through the sixth threshold adjustment regions are in contact with the second through the sixth source regions and with the second through the sixth drain regions, respectively.